/*
 * filename: RegFile.scala
 * description: 寻春CPU的寄存器组，两组读端口，一组写端口
 */
package XunChunCPU

import chisel3._
import XunChunCPU.common.Bundles._
import XunChunCPU.common.CommonConfig._
import chisel3.util._

class RegFile extends Module{
    val io = IO(new Bundle {
        // read port
        val read = new RegReadBundle
        // write port
        val write = new RegWriteBundle

    })
    val regs = RegInit(VecInit(Seq.fill(regNum)(0.U(regLen.W))))
    when(io.write.we && io.write.addr =/= 0.U) {
        regs(io.write.addr) := io.write.wdata
    }

    when(io.write.we && io.write.addr === io.read.rsAddr && io.write.addr =/= 0.U) {
        io.read.rsData := io.write.wdata
    } .otherwise {
        io.read.rsData := regs(io.read.rsAddr)
    }

    when(io.write.we && io.write.addr === io.read.rtAddr && io.write.addr =/= 0.U) {
        io.read.rtData := io.write.wdata
    } .otherwise {
        io.read.rtData := regs(io.read.rtAddr)
    }
}